RTL DESIGN ENGINEER

SmartSoC is looking for some expert RTL Front End Design Engineers, having good knowledge of ASIC design flow. This will be a very challenging and exciting role and will involve very complex designs.

Job Responsibilities-

1. Chip integration of high complexity SOCs.
2. Coordinating with various IP owners on receivables and DV, synthesis and Emulation for deliverables
3. Spyglass/CDC for the full chip and will evaluate the incoming bugs and take appropriate action
4. Formal Verification between RTL to Netlist and Netlist to Netlist
5. Manual and Conformal ECO
6. Running Lint (Spyglass) at SoC level.
7. Chip level integration and connectivity.
8. Debugging FV failures
9. ECO implementation.

Desired Skills and Experience-

1. 3 – 10 years of experience
2. Sound knowledge in Micro Architecture design and RTL implementation
3. Understanding of ARM SoCs with AXI/AHB buses, peripherals, CPUs and mobile SOCs is desirable.
4. Experience in Synthesis and pre-layout timing analysis
5. Understanding of DFT flow is desirable.
6. Experiencing using clear case a must
7. Experienced with VHDL/Verilog/coding and tools like VCS/Verdi/Spyglass/Mentor Zero-in
8. Proficiency in LEC and formal flows.
9. Experience in Perl, TCL and shell scripting
10. Excellent interpersonal & analytical skills with ability to work independently.