• 1-3 years of experience in RTL DFT Verification (DFx).

• Good Understanding of JTAG IEEE-1149.1 and IJTAG IEEE P1687 standard.

• Understanding of using ICL and PDL files for verification and knows to create a testbench.

• Experience in JTAG RTL verification within any UVM.

• Able to debug simulation fails effectively utilizing debug tools like Synopsis Verdi.

• Basics of system Verilog, Basics of UVM, and preferably System Verilog assertions • Scripting knowledge of TCL/Perl.