Digital Verification Engineer

Skills & Experience Required:

• 5+ years of relevant experience.
• Has relevant knowledge of wireline protocols, like USB, PCIe, DDR … etc.
• Extract verification requirements from system specification.
• Contribute to generating the verification plan for block level and system level.
• Contribute to architecting the verification environment which is mapped from the verification plan.
• Implement the verification environment using UVM.
• Debug test failures and work with designers to develop fixes.
• Work on achieving targeted coverage goal for the verification sign off.
• Perform post APR simulations.
• Provide guidance and mentoring to junior engineer.
• Excellent Knowledge of coverage driven verification concepts.
• Excellent Knowledge of any of the advanced verification methodologies (OVM/UVM/VMM).
• Excellent knowledge in verification environment architecting, designing and implementation.
• Good experience in developing and maintaining both block level and top-level verification environments for digital systems.
• Excellent debugging skills in both functional and gate level simulations.
• Experience with Assertion Based Verification languages (SVA, PSL…).
• Knowledge of any scripting language (PERL, TCL, Shell script, …)
• Experience with power aware verification and knowledge of writing of writing UPF. 
• Experience with Formal Verification.
• Knowledge of Co-simulation for digital and analog parts of the system using AMS simulators.
• in Shell, PERL, and Python.