We are seeking a highly skilled and experienced Lead Verification Engineer with expertise in USB/LPDDR and a strong knowledge of Cadence VIP. The ideal candidate will have a deep understanding of low-power design and verification techniques.

Responsibilities:

1. Develop and execute comprehensive verification strategies for USB/LPDDR subsystem designs, considering low-power design requirements. Collaborate with cross-functional teams to define verification goals and ensure alignment with project objectives.
2. Design and implement reusable, scalable, and efficient verification testbenches using SystemVerilog/UVM or C based . Leverage Cadence VIP and other verification IPs to accelerate the verification process.
3. Low-Power Design Verification: Apply expertise in low-power design and verification techniques to ensure accurate and reliable verification of power management features, including power states, power domains, and power-aware verification methodologies.

Requirements:

1. Extensive experience (8+ years) in verification.
2. Strong knowledge of Cadence VIP and verification methodologies (SystemVerilog/UVM).
3. Proficiency in low-power design techniques and power-aware verification methodologies.
4. Hands-on experience with industry-standard simulation and verification tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Questa).
5. Solid understanding of verification languages (SystemVerilog, VHDL) and scripting languages (Perl, Python, TCL).
6. Familiarity with industry standards and protocols related to USB (USB 2.0, USB 3.x) and LPDDR (LPDDR4, LPDDR5).