We are seeking a highly skilled and motivated Mixed Signal Verification Engineer to join our team with 8+ years of expeirence. As a Mixed Signal Verification Engineer, you will be responsible for developing and implementing testbenches, checkers, and tests using System Verilog. You will also play a key role in creating and utilizing real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Ownership of Analog/Mixed designs at the chip and/or block level will be an important aspect of this role.

Responsibilities:

• Develop and build Mixed-Signal testbenches, checkers, and tests using System Verilog.
• Create and utilize real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations.
• Take ownership of Analog/Mixed designs at the chip and/or block level, ensuring successful verification.
• Good Understanding of GLS simulations
• Collaborate with design engineers to understand design tradeoffs and create high-level models for design analysis.
• Perform behavioral modeling for verification simulations to validate the functionality and performance of mixed-signal designs.
• Debug and resolve issues arising from verification simulations and work closely with the design team to address any design-related concerns.
• Stay updated with the latest advancements in mixed-signal verification methodologies and tools, and drive continuous improvement initiatives.