Physical Design Engineer

1.       Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation

2.       Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology)

3.       Implementation of a project with the full Cadence tools

4.       Have worked on complex Hard macros with SerDes and/or critical in timing and area

5.       Having experience in Flip-Chip SoC bump Ios)

6.       Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file

Job Category: VLSI (Silicon engineering)
Job Type: Full Time
Job Location: India

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