RTL DESIGN LEAD ENGINEER

The ideal candidate will be required to work on both IP development and integration into SoCs catering to various markets and tech nodes. The job will involve RTL design, front-end tools flow, and SoC integration/porting-related tasks.

Desired Skills and Experience-

1. 8+ years of Experience
2. Engineering experience with exposure to front end ASIC tool flows
3. Should be self-driven and independent in tracking and closing tasks with respective holders. 
4. In depth knowledge of AHB and bus infrastructures like matrix and fabrics
5. Good understanding of ARM based SoC Architecture
6. Exposure to ARM Cortex A/M integration or support
7. Good understanding of SoC DV methodology
8. Good experience in Low-Power design methodology
9. Hands-on experience with ASIC tools Lint, CDC etc
10. System Verilog/Verilog RTL coding Power aware RTL coding/design knowledge
11. Understanding of Clock-Structures/Scheme Good Communication Skills