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SENIOR VERIFICATION ENGINEER – SV UVM

SmartSoC is looking for smart and enterprising Design Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting.  SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM.

Job Responsibilities-

  1.  Build SV, SV UVM, OVM based environments.
  2.  Work with many different networking and other protocols


Desired Skills and Experience-

  1. 3 to 10 years of experience in IP verification
  2. Good experience in SV/ UVM based verification project. Good debug skills is a must.
  3. Experience in building components like Scoreboard, functional coverage & writing sequences using SV/UVM based Verification environment
  4. One of the following experiences is important:
  5. Experience in Video/Display domain in particular DP, oLDI, MIPI CSI/ DSI
  6. Experience in any one high speed protocol like USB3, PCIe, MIPI, Unipro etc

Job Location: Finland: Oulu India: Bangalore India: Chennai India: Hyderabad India: Noida Malaysia Singapore Sweden: Stockholm USA: Delaware
Job Category: VLSI (Silicon engineering)

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