SR. DFT ENGINEER
SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board.
Desired Skills and Experience-
- 3 – 10 year’s experience in DFT
- Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.
- DFT logic integration and verification.
- Experience in debugging low coverage and DRC fixes
- Gate Level ATPG simulation with and without timing.
- Pattern generation, verification, and delivery to ATE team.
- Post silicon debug and support on failing patterns.
- Good experience with tools from Mentor/Synopsis/Cadence.
- LBIST experience is plus.
- DFT mode STA and timing closure support.
- Familiarity with Verilog and RTL simulation