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4th Floor Mobius Tower SJR I Park, Whitefield, Bangalore, Karnataka 560066

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Design Verification Engineer – Position 2

Experience: 5 to 12 years

Location: Bangalore

Job Description:

We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification and possess a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). This role specifically requires expertise in GLS (Gate-Level Simulation).

Key Responsibilities:

  1. IP and SOC Verification
  • Conduct IP and SOC verification activities to ensure the functionality and correctness of integrated circuits.
  1. SystemVerilog (SV) and UVM Proficiency
  • Demonstrate strong knowledge of SystemVerilog and Universal Verification Methodology for efficient and effective verification processes.
  1. Gate-Level Simulation (GLS)
  • Proficiency in Gate-Level Simulation is a mandatory requirement for this position.


  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 5 to 12 years of relevant industry experience in IP and SOC verification.
  • Strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM).
  • Proficiency in Gate-Level Simulation (GLS).

If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of integrated circuits, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology.

Job Category: VLSI (Silicon engineering)
Job Type: Full Time
Job Location: India: Bangalore

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