Analog Design Engineer

Skills & Experience Required:

• 5+ years of relevant experience.
• Has relevant knowledge and hands on experience of SerDes design at high data rates, up to 20Gbps.
• Study the assigned block, analyze the circuit carefully, and work on the hand analysis.
• Understand the required performance, the targeted specs and trade-off between different performance metrices.
• Write behavioral model of the circuit blocks for system-level simulations.
• Simulate and verifying designed schematics using Synopsys tools using circuit simulators.
• Debug to find out the root cause for any performance degradation.
• Being capable of solving all the faced issues.
• Working with layout team on layout optimization.
• Evaluate post layout performance using extraction tools (ICV and Calibre).
• Understand the interface with other blocks (if any) and work with other team members to optimize the interface.
• Coordinate and handling top-level simulations.
• Develop and executing characterization plans of the designed blocks, systems, and chips.
• Check the design reliability (EM/IR/Aging) using available tools.
• Do timing models using custom static timing analysis tools.
• Deliver the corresponding documentation as per the design process.
• Excellent knowledge of design/simulation tools such as Synopsys, Cadence and/or Mentor tools or any relevant tool.
• Good knowledge of any EM simulation tool.
• Good knowledge in behavioral modeling (Verilog, Verilog AMS).
• Very Good knowledge of custom timing static analysis tool (Synopsys NanoTime and SiliconSmart).