Discover how we’re driving innovation & adding significant value to businesses worldwide — and meet the people who make it possible.

Gallery

Contacts

4th Floor Mobius Tower SJR I Park, Whitefield, Bangalore, Karnataka 560066

info@smartsocs.com

+91 9606449635

DFT-DV

Number of Open Positions: 7

Experience: 4 to 7+ years

Location: Bangalore

Job Description:

We are seeking highly skilled and motivated DFT-DV Engineers to join our dynamic team in Bangalore. As a DFT-DV Engineer, you will play a pivotal role in ensuring the quality and reliability of our digital designs through Design for Test (DFT) and Design Verification (DV) methodologies. The ideal candidates should possess a minimum of 4 to 7+ years of experience in the field, with a strong background in DFT DV flow, JTAG, MBIST, SCAN, PG, PHY-LP, and BSCAN.

Key Responsibilities:

  1. DFT Implementation: Collaborate with design and verification teams to define and implement DFT strategies and methodologies that enable efficient testing of complex digital designs.
  2. Scan and ATPG: Develop and maintain scan insertion, Automatic Test Pattern Generation (ATPG), and compression methodologies to achieve high test coverage.
  3. Memory BIST: Implement and verify Memory Built-In Self-Test (MBIST) solutions for embedded memories in the design.
  4. JTAG and Boundary Scan: Develop JTAG and Boundary Scan solutions to facilitate efficient testing and debugging of digital designs.
  5. Power Management: Work on Power Gating (PG) techniques to optimize power consumption during testing.
  6. PHY-LP Integration: Collaborate with PHY teams to ensure seamless integration of low-power features into the design.
  7. BSCAN Integration: Implement Boundary Scan (BSCAN) infrastructure to enhance testability and debug capabilities.
  8. Verification: Verify DFT features and ensure their correctness through simulation and formal verification.
  9. Documentation: Prepare detailed documentation, including DFT specifications, test plans, and reports.

Qualifications:

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field.
  • 4 to 7+ years of experience in DFT-DV engineering.
  • Strong expertise in DFT methodologies, including scan, ATPG, MBIST, JTAG, BSCAN, and PG.
  • Proficiency in industry-standard EDA tools for DFT implementation.
  • Experience with low-power design and PHY-LP integration is a plus.
  • Excellent problem-solving skills and attention to detail.
  • Strong communication and teamwork skills.

If you are a proactive and results-oriented engineer with a passion for ensuring the quality and reliability of digital designs, we encourage you to apply. Join us in our mission to develop cutting-edge technology and make a significant impact in the semiconductor industry.

Job Category: VLSI (Silicon engineering)
Job Type: Full Time
Job Location: India: Bangalore

Apply for this position

Allowed Type(s): .pdf, .doc, .docx

Author

SmartSoC

Translate »