Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech)
• Excellent communication skills, both verbal and written

Experience:

• 5-8 years of experience in RTL Design with exposure to synthesis OR 8+ years of experience in RTL Design
• Strong understanding of digital basics
• Proficiency in RTL coding (Verilog), IP design, and RTL integration
• Hands-on experience with LINT, CDC, and RDC
• Experience in writing UPFs and CLP/VCLP checks
• Familiarity with synthesis flow and validating design constraints
• Specific domain knowledge in ARM protocols, PCIe, Ethernet, RISC V, DDR, etc.
• Strong scripting knowledge

Responsibilities:

• Understand the overall ASIC flow and effectively collaborate with multiple teams such as DV, DFT, Synthesis/Implementation, and PD teams
• Ability to take on the role of a Technical Manager while maintaining hands-on contributions

Note: Interested candidates should provide a detailed resume highlighting relevant experience and skills.